To provide power to an integrated circuit device (e.g., chip), a chip typically includes an input receiver for a power supply voltage. To better understand various aspects of the disclosed embodiments of the invention, a number of conventional input receiver arrangements will be described.
A first conventional chip input receiver arrangement will now be described with reference to FIG. 8. FIG. 8 shows a chip designated by the general reference character 800. A chip 800 can receive an external power supply voltage VCC at a power supply input pad 802. In addition, an input signal (in) can be received at a corresponding signal input pad 804. Chip 800 also provides an internal supply voltage VPWR, which can be generated by a voltage regulator 806. Such an internal supply voltage can be provided to an internal portion 808 of chip 800.
An input receiver 810 can receive input signal (in), and in response thereto, provide an output signal (out) to internal portion 808. It is understood that input receiver 810 may include voltage translator circuits that can ensure that output signal out stays within an internal power supply range, which in this case is from VPWR to ground.
As shown in FIG. 8, input receiver 810 receives a high power supply voltage VCC power from an external source (i.e., power supply input pad 802), and circuits within input receiver 810 operate between a VCC potential and a lower power supply potential (e.g., ground). As will be described at a later point herein, such an arrangement, depending the relative level levels of VCC and input signal in, may have undesirable static and active current consumption.
A second conventional example is shown in FIG. 9. FIG. 9 includes the same general arrangement as FIG. 8, thus like components are referred to by the same reference characters but with the first digit being a “9” instead of an “8”.
The arrangement of FIG. 9 differs from that of FIG. 8 in that input receiver 910 receives an internally generated power supply VPWR. Circuits within input receiver 910 operate between a VPWR potential and a lower power supply potential (e.g., ground). This arrangement may also have undesirable static and active current consumption. Such drawbacks will also be described at a later point herein.
Accordingly, the above arrangements may not be optimal, especially for applications that may require multiple power supply configurations. One or more of these configurations will likely draw excessive current. An example of a chip that might require multiple power supply configurations is where a single die includes multiple die options to serve various markets. These configurations can be chosen by permanent selection methods, such as bond-options, fuse-options, or metal options, and the like. Further, a chip may provide one power supply level for input/output (I/O) pins, while generating a different internal power supply.
A third conventional example is shown in FIG. 10 and includes some of the same general components as FIG. 8. Accordingly, like components are referred to by the same reference characters but with the first digit being a “10” instead of an “8”.
Unlike the arrangement of FIG. 8, in FIG. 10 multiple input receivers 1010-0 and 1010-1 are provided for each signal input pad 1004. One input receiver circuit (e.g., 1010-0 or 1010-1) can be permanently enabled while the other is permanently disabled according to a desired option.
A first drawback to the arrangement such as that shown in FIG. 10 can be the increased layout area required in forming two input receivers as opposed to only one. This can increase production costs. A second drawback can be that an input signal is applied to multiple receiver circuits, resulting in higher input capacitance. A third drawback can be that there is typically not much flexibility in which receiver is selected. That is, a given configuration will be permanently set to either one receiver or the other, perhaps by the bond arrangement, fuse blowing, or metal means, and the like.
In light of the above, it would be desirable to arrive at some form of input receiver that can accommodate multiple power supplies, but not suffer from the drawbacks of the above conventional approaches, such as high standby and active currents, large circuit layout area, and high pin input capacitance.